4 fpga register mapping, 1 lpc i/o register map, 2 ipmc spi register map – Artesyn ATCA-7365 Installation and Use (November 2014) User Manual
Page 196: 1 lpc i/o register map 6.4.2 ipmc spi register map, Table 6-40, Fpga register map overview, Maps and registers
Maps and Registers
ATCA-7365 Installation and Use (6806800K65N)
196
6.4
FPGA Register Mapping
6.4.1
LPC I/O Register Map
The FPGA registers may be accessed via LPC I/O cycles in the I/O address range REGISTERS. For
LPC register access, use the base address 0x600 and add the Address Offset. An LPC I/O write
access to an address not listed in
or not marked with an “X” in the LPC I/O column is
ignored. A corresponding read access delivers always zero.
LPC I/O Address = 0x600 + Address Offset
6.4.2
IPMC SPI Register Map
The FPGA registers may be accessed via IPMC SPI transactions (with the signal
IPMC_SPI_SS_FPGA_ asserted). A SPI write access to an address not listed in this table or not
marked with an “X” in the IPMC SPI column is ignored. A corresponding read access delivers
always zero.
Table 6-40 FPGA Register Map Overview
Address
Offset
1
LPC I/O
IPMC
SPI
Description
0x00
x
x
Module Identification Register
0x01
x
x
FPGA Version Register
0x03 - 0x05
x
x
Serial Line Routing Registers
0x06
x
x
IPMC Power Level Register
0x08
x
x
SPD PROM MUX Control Register
0x10
x
x
BIOS Reset Source Register
0x11
x
x
Reset Mask Register
0x12
x
x
BIOS IPMC Watch dog timeout Register
0x13
x
-
BIOS Push Button Enable Register
0x14
x
x
OS Reset Source Register