Artesyn ATCA-7365 Installation and Use (November 2014) - Manual (Page 193)

Maps and Registers
ATCA-7365 Installation and Use (6806800K65N) 193
When bits 0, 1, 2, or 3 are set to logic 1, a Modem Status interrupt is generated if bit 3 of the
Interrupt Enable Register is set.
Table 6-36 Modem Status Register (MSR)
LPC IO Address: Base + 6
Bit Description Default Access
0 Change in clear-to-send (DCTS) indicator
DCTS indicates that the CTS# input has changed state since
the last time it
was read by the CPU. When DCTS is set (autoflow control is
not enabled and the modem status interrupt is enabled), a
modem status interrupt is generated. When autoflow
control is enabled (DCTS is cleared), no interrupt
is generated:
1: Change in state of CTS# input since last read
0: No change in state of CTS# input since last read 0 LPC: r/w
1 Change in data set ready (DDSR) indicator
DDSR indicates that the DSR# input has changed state since
the last time it
was read by the CPU. When DDSR is set and the modem
status interrupt is
enabled, a modem status interrupt is generated:
1: Change in state of DSR# input since last read
0: No change in state of DSR# input since last read 0 LPC: r/w
2 Trailing edge of the ring indicator (TERI) detector
TERI indicates that the RI# input to the chip has changed
from a low to a high level. When TERI is set and the modem
status interrupt is enabled, a modem status interrupt is
generated. Not supported. 0 LPC: r/w
3 Change in data carrier detect (DDCD) indicator
DDCD indicates that the DCD# input to the chip has
changed state since the
last time it was read by the CPU. When DDCD is set and the
modem status
interrupt is enabled, a modem status interrupt is generated.
Not supported. 0 LPC: r/w