Artesyn ATCA-7365 Installation and Use (November 2014) - Manual (Page 217)

Maps and Registers
ATCA-7365 Installation and Use (6806800K65N) 217
Write protection status signals for the Boot SPI flashes are determined by external switch
settings SW1.1and SW1.2. Software can overwrite the status of the write protection status by
writing a magic word to the Boot SPI Flash Write Enable Registers.
6.4.14 BIOS Boot Mode Register
The following table provides a detailed description about BIOS Boot Mode Register.
Table 6-65 Default Boot SPI Flash Write Enable
Address Offset: 0x41
Bit Description Default Access
7:0 Default Boot SPI Flash Write enable/disable.
A write value 0xC3 enables the Boot Block. All other
values disables the Boot Block - LPC: w
Table 6-66 Recovery Boot SPI Flash Write Enable
Address Offset: 0x42
Bit Description Default Access
7:0 Recovery Boot SPI Flash enable/disable.
A write value 0xC3 enables the Flash. All other values
disables the Flash - LPC: w
Table 6-67 BIOS Boot Mode Register
Address Offset: 0x43
Bit Description Default Access
0
The switch signals SW_BIOS[1:0] controls the BIOS
Boot Mode:
-Ext.
1: SW4.3 ON
0: SW4.3 OFF