Artesyn ATCA-7365 Installation and Use (November 2014) - Manual (Page 155)

Functional Description
ATCA-7365 Installation and Use (6806800K65N) 155
5.3.1 Persistent memory (PMEM Module)
The blade supports a persistent memory. The persistent memory is an array of random access
memory that preserves its contents during a payload reset. The memory is mapped into the
memory address range of the CPU. Persistent memory is a necessary prerequisite for
performing post mortem analysis of log data after reset and reboot of the payload CPU
5.4 Chipset
The Intel 5520 chipset provides access between the two processors and the I/O subsystem. The
chipset provides up to 36 PCI Express Generation 2 lanes. The blade makes use of 5 times x4
PCIe lanes routed to the Zone 3 connector.
The chipset is connected to the ICH10R I/O Controller via the Enterprise South Bridge Interface
(ESI).
5.5 I/O Controller
The ICH10R provides extensive I/O interface support and the BOOT path to SPI Boot Flash
devices for the processor. ICH10R is connected to the system through the Enterprise
Southbridge Interface (ESI) of the Xeon 5520 chipset.
The following is a list of the main internal features and the I/O interface functions provided by
the ICH10R Southbridge:
 Six x4 PCI Express 1.1 Interface
 LPC interface
 SPI Interface (Boot Flash): up to two devices 20 + 33 MHz
 Six serial ATA (SATA) interfaces (2 used on ATCA-7365)
 Twelve USB 2.0 interfaces (4 used on ATCA-7365)
 Two 8259 Interrupt Controllers and I/O APIC controllers
 Integrated I/O APIC
 Power management support
 Two 8237 DMA controllers