Artesyn ATCA-7365 Installation and Use (November 2014) - Manual (Page 184)

Maps and Registers
ATCA-7365 Installation and Use (6806800K65N) 184
6.3.4.2.5 FIFO Control Register (FCR)
FCR is a write-only register that is located at the same address as the IIR (IIR is a read-only
register). FCR enables/disables the transmitter/receiver FIFOs, clears the transmitter/receiver
FIFOs, and sets the receiver FIFO trigger level.
7:6 FIFO Mode Enable bits:
00: Default mode
01: Reserved
10: Reserved
11: FIFO mode 0 LPC: r
Table 6-31 Interrupt Identification Register (IIR) (continued)
LPC IO Address: Base + 1
Bit Description Default Access
Table 6-32 FIFO Control Register (FCR)
LPC IO Address: Base + 2
Bit Description Default Access
0 FIFO enable/disable:
1: Transmitter and Receiver FIFO enabled
0: FIFO disabled 0 LPC: w
1 Receiver FIFO reset:
1: Bytes in receiver FIFO and counter are reset.
Shift register is not reset
(bit is self-clearing)
0: No effect 0 LPC: w
2 Transmit FIFO reset:
1: Bytes in receiver FIFO and counter are reset.
Shift register is not reset
(bit is self-clearing)
0: No effect 0 LPC: w
3 Receiver/Transmitter ready. Not supported. 0 LPC: w
5:4 Reserved 0 LPC: w