Maxim Integrated 71M6513H Power Meter IC Family Software - Manual (Page 97)

71M651x Software User’s Guide
6.2.80515 ARCHITECTURAL OVERVIEW
6.2.1. Memory organization
The 80515 Micro controller core incorporates the Harvard architecture with separate code and data spaces.
Memory organization in the 80515 is similar to that of the industry standard 8051. There are three memory areas:
program memory (External Flash or ROM), external data memory (External RAM), and internal data memory (Internal
RAM).
Figure 6-1: Memory Map
Program Memory
The 80515 can address up to 64kB of program memory space from 0000H to FFFFH. Program memory is read when
the MPU fetches instructions or performs a MOVC.
After reset, the MPU starts program execution from location 0000H. The lower part of the program memory includes a
reset and interrupt vectors. The interrupt vectors are spaced at 8-byte intervals, starting from 0003H.
External Data Memory
The 80515 can address up to 64kB of external data memory in the space from 0000H to FFFFH. The 80515 writes
into external data memory when the MPU executes a MOVX @Ri,A or MOVX @DPTR,A instruction. The external data
memory is read when the MPU executes a MOVX A,@Ri or MOVX A,@DPTR instruction.
There is an improved variable length access for the MOVX instructions to access fast or slow external RAM and
external peripherals. The three low ordered bits of the CKCON register define the stretch memory cycles. Setting all
the CKCON stretch bits to one allows access to very slow external RAM or external peripherals.
Table 6-2 shows how the signals of the External Memory Interface change when stretch values are set from 0 to 7.
The widths of the signals are counted in MPU clock cycles. The post-reset state of the CKCON register, which is in
bold in the table, performs the MOVX instructions with a stretch value equal to 1.
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Program memory
FFFFH
0000H
External data memory
8000H
4000H
C000H
00H
FFH
Internal data memory
FFFFH
0000H
8000H
4000H
C000H