Maxim Integrated 71M6513H Power Meter IC Family Software - Manual (Page 66)

71M651x Software User’s Guide
5.3.4. Watchdog Timer
The Demo Code revision 3.04 uses only the hardware watchdog timer provided by the 80515. This fixed-duration
timer is controlled with SFR register WDI (0xE8).
The software watchdog timer is described in section 6.3.4, but should not be used. The hardware watchdog
timer is more reliable since it cannot be accidentially disabled.
The hardware watchdog timer requires a refresh by the MPU firmware, i.e. bit 7 of WDI set, at least every 1.5
seconds. If this refresh does not occur, the hardware watchdog timer overflows, and the 80515 is reset as if RESETZ
were pulled low. When overflow occurs, the bit WD_OVF is set in the configuration RAM. Using the WD_OVF bit, the
MPU can determine whether a reset or a hardware watchdog timer overflow occurred. The WD_OVF bit is cleared
when RESETZ is pulled low.
The bits of the WDI register (SFR 0xE8) should not be individually set or reset. Instead, byte operations
should be used.
The following macro code should be used for resetting (clearing) the watchdog, IE_RTC or IE_XFER bits:
#define WD_RST_ 0xFF // WatchDog bit.
#define IE_RTC_ 0x02 // RTC ticked.
#define IE_XFER_ 0x01 // XFER data available.
#define RESET_WD() WDI = WD_RST_;
#define CLR_IE_XFER() WDI = ~ IE_XFER_ & 0x7F ; // 0x7E
#define CLR_IE_RTC() WDI = ~ IE_RTC_ & 0x7F ; // 0x7D
5.3.5. Real-Time Clock (RTC)
The RTC is accessible through the I/O RAM (Configuration RAM) registers RTC_SEC through RTC_YR
(addresses 0x2015 through 0x201B), as decribed in the data sheets.
Since the RTC runs on a much slower clock than the MPU, only one write operation can be performed per
RTC clock cycle. This means that write operations to set the RTC must be separated by at least 396us.
The sample code uses hardware timer 1 to perform this delay, so any code modification must make sure
that hardware timer 1 is still useable for the RTC functions.
5.4.DATA FLOW
The ADC collects data from the electrical inputs on a cycle that repeats at 2520Hz. On each ADC cycle, the compute
engine (CE) code digitally filters and adjusts the data using gain parameters (CAL_Ix, CAL_Vx) and phase adjustment
parameters (PHADJ_x). Also, it adjusts for temperature using the linear (PPMC) and squared (PPMC2) temperature
gain coefficients and a nominal temperature of calibration (TEMP_NOM).
Normally, a calibration operation during manufacturing finds these adjustments and stores them in flash or EEPROM
to be placed into CE memory. The Demo Code includes a basic linear self-calibration function that can typically reach
0.05% accuracy. (ce.c: ce_update(), cal.c: cal_begin(), calibration() ).
Better calibration schemes are routinely possible. The calibration save and restore operations (cal_save() and
cal_restore() ) save and restore all adjustment variables, such as the constants for the real-time clock, not just the
ones for electrical measurements.
On each ADC cycle, 2520 times per second, the CE performs the following tasks:
1. It calculates intermediate results for that set of samples.
2. It runs a debounced check for sagging mains, with a configurable debounce.
3. It has three equally-spaced opportunities to pulse each pulse output.
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