Maxim Integrated 71M6513H Power Meter IC Family Software - Manual (Page 123)

71M651x Software User’s Guide
6.3.4. Software Watchdog Timer
The watchdog timer is a 16-bit counter that is incremented once every 24 or 384 clock cycles. After an external reset,
the watchdog timer is disabled and all registers are set to zero.
Software Watchdog Timer structure
The watchdog consists of a 16-bit counter (wdt), a reload register (WDTREL), prescalers (by 2 and by 16), and control
logic.
Figure 6-3: Watchdog Block Diagram
WD Timer Start Procedure
During an active internal rst signal, the programmer can start the watchdog later. It will occur when the swd signal
becomes active. Once the watchdog is started, it cannot be stopped unless the internal rst signal becomes active.
When the wdt registers enters the state 0x7CFF , an asynchronous wdts signal will become active. The signal wdts
sets bit 6 in the IP0 register and requests a reset state. Wdts is cleared either by the rst signal or changing the state of
the wdt timer.
Refreshing the WD Timer
The watchdog timer must be refreshed regularly to prevent the reset request signal from becoming active. This
requirement imposes an obligation on the programmer to issue two instructions. The first instruction sets wdt and the
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2
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16
wdtl wdth
wdtrel
Control
logic
fclk/12
wdts
swd
wdt
swdt
0 7 8 14
7 6 0