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80515 reference, 80515 overview, 80515 performance – Maxim Integrated 71M6513H Power Meter IC Family Software User Manual

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71M651x Software User’s Guide

6. 80515 REFERENCE

An 80515 core is implemented on the TERIDIAN 71M651X chips. This section is intended for software engineers who
plan to use the 80515.

6.1.80515 OVERVIEW

The 80515 is a fast single-chip 8-bit micro controller core. It is a fully functional 8-bit embedded controller that
executes all ASM51 instructions and has the same instruction set as the 80C31. The 80515 provides software and
hardware interrupts, an interface for serial communications, a timer system and a watchdog timer.

6.1.1. 80515 Performance

The architecture eliminates redundant bus states and implements parallel execution of fetch and execution phases.
Normally a cycle is aligned with a memory fetch, therefore, most of the 1-byte instructions are performed in a single
cycle. The 80515 uses 1 clock per cycle leading to an 8x performance improvement (in terms of MIPS) over the Intel
8051 device running at the same clock frequency.

The original 8051 had a 12-clock architecture. A machine cycle needed 12 clocks and most instructions

were either one or two machine cycles. Thus, except for the MUL and DIV instructions, the 8051 used

either 12 or 24 clocks for each instruction. Furthermore, each cycle in the 8051 used two memory fetches.

In many cases the second fetch was a dummy, and extra clocks were wasted.

Table 6-1 shows the speed advantage of the 80515 over the standard 8051. A speed advantage of 12 means that the
80515 performs the same instruction twelve times faster that the 8051.

Speed advantage

Number of

instructions

Number of

opcodes

24

1

1

12

27

83

9.6

2

2

8

16

38

6

44

89

4.8

1

2

4

18

31

3

2

9

Average: 8.0

Sum: 111

Sum: 255

Table 6-1: Speed Advantage Summary

The average speed advantage is 8x, however, the actual speed improvement observed in a system will depend on the
instruction mix.

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