Rockwell Automation SA500 Drive Configuration and Programming - Manual (Page 84)

3-52 SA500 Drive Configuration and Programming
Interrupt Status Control Registers (Continued) 2000
CCLK Counting Bit 5
Hex Value: 0010H
Sug. Var. Name: N/A
Access: Read only
UDC Error Code: N/A
LED:
N/A
Enable CCLK Bit 6
CCLK must be enabled for the UDC module
to execute its task(s) and communicate
synchronously with the PMI. Hex Value: 0001H
Sug. Var. Name: UDC_CCLK_ENA@
Access:
Read/Write
UDC Error Code: N/A
LED:
N/A
Only one module per rack should enable CCLK. If CCLK is enabled on multiple
modules in the rack, an overlap error will result (error code 38). Other modules that
can enable CCLK include the M/N 57C409, 57C421, and the 57C411.
The UDC module uses CCLK to determine when it should run its tasks. CCLK is also
used as the time reference for all UDC modules in the rack so that they are all
synchronized to start at specific time periods. If interrupts to the AutoMax Processor
are required, register 2001 must be set to the desired value before CCLK is enabled.
Interrupt Enabled Bit 7
The Interrupt Enabled bit, when set by the
operating system, indicates that a hardware
EVENT has been defined in an AutoMax
task. Hex Value: 0001H
Sug. Var. Name: N/A
Access: Read only
UDC Error Code: N/A
LED:
N/A
No other programming is required for the UDC operating system to generate an
interrupt in the interval defined in register 2001.
Interrupt Status Bit 15
The Interrupt Status bit is set to indicate that
an interrupt is being generated at this time. Hex Value: 0001H
Sug. Var. Name: N/A
Access: Read only
UDC Error Code: N/A
LED:
N/A