Rockwell Automation SA500 Drive Configuration and Programming - Manual (Page 49)

Configuring the UDC Module’s Registers 3-17
3.3 Command Registers (Registers 100-149/1100-1149)
The Command Registers view is used to configure command registers. These
registers are used for command data sent to the PMI by the UDC module at the end of
every scan of the UDC Processor. Note that the bits in these registers (except bit 15
in register 100/1100) are used to command action only and do not indicate the status
of the action commanded. The feedback registers (registers 200/1200 to 299/1299)
are provided for this purpose. The status of the command registers is not retained
after a Stop All.
The Command Registers view is also used to configure the volatile gain registers
(registers 150/1150 to 199/1199). See section 3.4
for more information.
.
Drive Control Register 100/1100
The Drive Control Register contains the bits that control the operation of the drive. All bits in this register
(except bit 15) can only be written to by a task on an AutoMax Processor. They cannot be written to by a task
on a UDC module. All read/write bits in this register are edge-sensitive.
Enable PMI Loop Bit 0
The Enable PMI Loop bit is set to enable the
motor regulation minor loop in the PMI. This
will be vector or brushless, depending on
which control algorithm (regulator) was
configured. Hex Value: 0001H
Sug. Var. Name: PMI_RUN@
Access: Read/Write
UDC Error Code: N/A
LED:
N/A
Resolver Alignment Test Bit 1
The Resolver Alignment Test bit is set to
enable the resolver alignment procedure.
This procedure is used for brushless drives
only. Hex Value: 0002H
Sug. Var. Name: ALN_TST@
Access: Read/Write
UDC Error Code: N/A
LED:
N/A
This procedure automatically determines the offset required to bring the rotor and
stator fields 90° apart. This procedure will cause the motor to move less than
one revolution in both forward and reverse direction for less than one minute.
Uncouple the motor from the load to run this test if this motion would be
harmful to your machine.
The result of this test is written to the tunable variable RES_ALN% by the PMI.
When the alignment procedure is successfully completed, the PMI will set the
Alignment OK bit (register 200/1200, bit 1). The user can then turn off the Enable
Resolver Alignment Test bit. This will also turn off the Alignment OK bit.
If a problem is detected during the alignment procedure, then the Tuning Aborted
Warning bit (register 203.1203, bit 5) is set. Refer to Appendix B for more
information regarding local tunable RES_ALN%.