Rockwell Automation SA500 Drive Configuration and Programming - Manual (Page 50)

3-18 SA500 Drive Configuration and Programming
Drive Control Register (Continued) 100/1100
Speed Loop On Bit 3
The Speed Loop On bit is set to enable the
PMI speed loop. This bit must be set for the
position loop (see bit 4) to run. All speed
loop variables are reset when this bit is
turned off. Hex Value: 0008H
Sug. Var. Name: SPD_ON@
Access: Read/Write
UDC Error Code: N/A
LED:
N/A
Position Loop On Bit 4
The Position Loop On bit is set to enable to
PMI position loop. The Speed Loop Enable
bit (see bit 3) must also be set. All position
loop variables are reset when this bit is
turned off. Hex Value: 0010H
Sug. Var. Name: POS_ON@
Access: Read/Write
UDC Error Code: N/A
LED:
N/A
Fault Reset Bit 8
The Fault Reset bit is set and reset to clear
the Drive Fault register, 202/1202. After a
drive fault is latched, the Drive Fault register
must be cleared before the drive can be
re-started. Hex Value: 0100H
Sug. Var. Name: FLT_RST@
Access: Read/Write
UDC Error Code: N/A
LED:
N/A
To clear the Drive Fault register any command bits that have been set in the Drive
Control register (100/1100) must first be turned off. Once the cause of the fault has
been corrected, the Fault Reset bit must be turned on and then off again. The Fault
Reset bit will clear the entire Drive Fault register. Then the desired command bits
may be turned on again.
The Fault Reset bit is edge-sensitive, i.e., leaving it set will not clear the fault register
continuously. Note that if the fault condition still exists after register 202/1202 is
cleared, it will continue to trigger drive faults until the problem has been corrected.
Warning Reset Bit 9
The Warning Reset bit is set and reset to
clear the Drive Warning register
203/1203. This bit is edge-sensitive, i.e.,
leaving it set will not clear the warning
register continuously. Hex Value: 0200H
Sug. Var. Name: WRN_RST@
Access: Read/Write
UDC Error Code: N/A
LED:
N/A