Rockwell Automation SA500 Drive Configuration and Programming User Manual
Page 41
![background image](/manuals/581510/41/background.png)
Configuring the UDC Module’s Registers
3-9
3.3
UDC/PMI Communication Status Registers
(Registers 80-89/1080-1089)
The UDC/PMI Communication Status Registers display the status of the fiber-optic
communications between the UDC module and the PMI. Two consecutive errors will
be indicated by a communication fault, and the drive will stop. Refer to register
202/1202, bit 15, for more information. Note that the communication status registers
are for system use only and can only be monitored. They cannot be defined during
configuration for access within the application task. The status of these registers will
be retained after a STOP ALL.
UDC Module Ports A/B Status Register
80/1080
The UDC Module Ports A/B Status register contains bits which describe any errors or warnings reported on
the UDC module related to UDC/PMI communication on port A and port B. These bits are latched when set
and will remain set until a fault reset or warning reset is issued.
Invalid Receive Interrupt
Bit 0
The Invalid Receive Interrupt bit is set if the
interrupt generated by the Universal Serial
Controller (USC) is not properly marked.
Hex Value:
0001H
Sug. Var. Name:
N/A
Access:
Read only
UDC Error Code: N/A
LED:
N/A
No End of Frame Status Received
Bit 1
The No End of Frame Status Received bit is
set if the USC does not report an End of
Frame condition when the receive interrupt
is generated.
Hex Value:
0002H
Sug. Var. Name:
N/A
Access:
Read only
UDC Error Code: N/A
LED:
N/A
CRC/Framing Error
Bit 2
The CRC/Framing Error bit is set if the USC
reports a CRC or Framing error on the last
frame (message) received.
Hex Value:
0004H
Sug. Var. Name:
N/A
Access:
Read only
UDC Error Code: N/A
LED:
N/A
Overrun Error
Bit 3
The Overrun Error bit is set if the USC
reports a receive first-in, first-out overrun.
Hex Value:
0008H
Sug. Var. Name:
N/A
Access:
Read only
UDC Error Code: N/A
LED:
N/A