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Ppendix, Sa500 drive register reference – Rockwell Automation SA500 Drive Configuration and Programming User Manual

Page 101

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SA500 Drive Register Reference

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PPENDIX

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SA500 Drive Register Reference

REGISTER MAP

Registers

Function

0-23

Rail I/O port registers

24-79

System Use Only

80-89

UDC/PMI comm. status registers for drive A

90-99

System Use Only

100-108

Command registers for drive A

109-149

System Use Only

150-199

Volatile gain registers for drive A

200-221

Feedback registers for drive A

222-299

System Use Only

300-599

Application registers updated every scan
for drives A and B

600-999

System Use Only

1000

UDC module test switch register

1001-1017

UDC module meter port setup registers

1018-1079

System Use Only

1080-1089

UDC/PMI comm. status registers for drive B

1090-1099

System Use Only

1100-1108

Command registers for drive B

1109-1149

System Use Only

1150-1199

Volatile gain registers for drive B

1200-1221

Feedback registers for drive B

1222-1299

System Use Only

1300-1599

Application registers updated every scan
for drives A and B

1600-1999

System Use Only

2000-2010

Interrupt Status and Control registers for
drives A and B

2011-2047

System Use Only

REGISTER/BIT DESCRIPTIONS

Rail I/O PORT REGISTERS

A / B
0 / 12

PMI port 0, channel 0

1 / 13

PMI port 0, channel 1

2 / 14

PMI port 0, channel 2

3 / 15

PMI port 0, channel 3

4 / 16

PMI port 0 faults (see below)

5 / 17

PMI port 0 check bit fault counter

6 / 18

PMI port 1, channel 0

7 / 19

PMI port 1, channel 1

8 / 20

PMI port 1, channel 2

9 / 21

PMI port 1, channel 3

10 / 22

PMI port 1 faults (see below)

11 / 23

PMI port 1 check bit fault counter

RAIL FAULT BITS (Registers 4/16 and 10/22)

Bit
0 Analog ch. 0 input over-range
1 Analog ch. 0 input under-range
2 Analog ch. 1 input over-range
3 Analog ch. 1 input under-range
4 Analog ch. 2 input over-range
5 Analog ch. 2 input under-range
6 Analog ch. 3 input over-range
7 Analog ch. 3 input under-range
8 No device plugged into configured port
9 Bad ID code
10 Bad rail comm. check bits received
11 PMI processor interface not ready

UDC-PMI COMMUNICATION STATUS

A/B
80 /1080 UDC ports status

Bit
0 Invalid receive interrupt
1 No end of frame status received
2 CRC/framing error
3 Overrun error
4 DMA format error
5 Transmitter underrun
6 CCLK communication synch error
7 External loopback data error
8 Missed gains
9 Multiplexed data verification error
10 No matching PMI OS present
11 Invalid PMI OS header
12 Incompatible PMI hardware

81 /1081 UDC good message received count

82 /1082 UDC CRC error count

83 /1083 UDC format error count

84 /1084 PMI communication status

Bit
0 Invalid receive interrupt
1 No end of frame status
2 CRC/framing error
3 Overrun error
4 DMA format error
5 Transmitter underrun
6 CCLK communication synch error
8 UDC CCLK communication synch error
9 Multiplexed data verification error
12 Invalid PMI start OS address
13 Insufficient PMI memory to load PMI OS
14 Invalid PMI load address
15 PMI OS overflow

85 /1085 PMI good message received count

86 /1086 PMI CRC error count

87 /1087 PMI format error count

88 /1088 Fiber-optic link communication status

89 /1089 UDC transmitted message count

COMMAND REGISTERS

A/B

100/1100 Drive Control

Bit
0 Enable PMI loop

PMI_RUN@

1 Resolver alignment test

ALN_TST@

3 Speed loop on

SPD_ON@

4 Position loop on

POS_ON@

6 (reserved for future use)

SPD_TUN@

8 Fault reset

FLT_RST@

9 Warning reset

WRN_RST@

10 Enable notch filter

NTCH_EN@

15 UDC task running (status)* UDC_RUN@
*Bit 15 in register 100/1100 must not be written

to by the programmer. All other bits in 100/1100
are read/write.

COMMAND REGISTERS (Continued)

A/B

101/1101 I/O Control

Bit
0 Stop intrpol fld ref crv

NO_INTR@

2 External fault LED

EXT_LED@

4 Auxiliary output

AUX_OUT@

6 Enable resolver bal calib

RES_CAL@

8 Enable external strobe

STR_ENA@

9 Enable ext strb falling edge STR_ENF@
10 Calculate Iz value

TUNE_IZ@

15 UDC loopback test

UDC_LB@

102/1102 External torque reference

TRQ_REF%

105/1105 Speed reference into ramp

SPD_STPT%

106/1106 Position reference

POS_STPT%

107/1107 Speed reference no ramp

SPD_REF%

108/1108 Position feedback from UDC

EXT_POS_FB%

109/1109 External reference flux wkn

EXT_CP_REF%

VOLATILE GAIN REGISTERS

SPEED LOOP VARIABLES

A/B

150/1150 Speed loop crossover freq

WCOS%

151/1151 Speed loop damping factor

ZETAS%

152/1152 Speed loop rate limit

SPD_RATE%

153/1153 Speed loop feed forward

SPD_FF%

154/1154 Notch filter center frequency

NTCH_W%

155/1155 Notch filter Q factor

NTCH_Q%

156/1156 Tach loss max velocity error SPD_ERR_THR%
157/1157 Speed loop inertia scaling

J_SCALE%

POSITION LOOP VARIABLES

A/B

160/1160 Position loop crossover freq

WCOP%

161/1161 Position loop damping factor

ZETAP%

162/1162 Position loop rate limit

POS_RATE%

163/1163 Position loop feed forward

POS_FF%

164/1164 Position loop limit plus

POS_LP%

165/1165 Position loop limit minus

POS_LM%

166/1166 Tach loss max position error POS_ERR_THR%

FEEDBACK REGISTERS

A/B

200/1200 Drive status

Bit
0 Drive enable grant

PMI_ON@

1 Resolver alignment OK

ALN_OK@

2 Torque ref in positive limit

TRQ_SP@

3 Torque ref in negative limit TRQ_SM@
4 Positive position limit

POS_SP@

5 Negative position limit

POS_SM@

6 (reserved for future use)

SPD_OK@

8 Fault detected

FLT@

9 Warning detected

WRN@

10 Notch filter enabled

NTCH_ON

11 Torque loop ref in pos sat

TRF_SP@

12 Torque loop ref in neg sat

TRF_SM@

14 CCLK synched (PMI/UDC) CCLK_OK@
15 PMI OS loaded

PMI_OK@