Teledyne LeCroy TA660СА - Manual (Page 126)

TA660 User's Manual Catalyst Enterprises, Inc
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ERR31 DEVSEL# was asserted during special cycle. PCI Rev 2.2. - 3.6.2
ERR32 PAR does not match parity across AD[31:0] and CBE[3:0] (TA660A only
ERR33 PAR64 does not match parity across AD[63:32] and CBE[7:4] (TA660A only),
ERR34 IRDY# was asserted on the same clock edge that FRAME# was asserted. PCI Rev 2.2.
3.3.1.Read Transaction
ERR35 DEVSEL# was asserted before FRAME# was asserted. PCI Rev 2.2-3.3.1 and 3.3.2
ERR36 IRDY# was asserted when FRAME# was high. PCI Rev 2.2- Appendix C, Rule 7
ERR37 After IRDY# was asserted, IRDY# or FRAME# were changed before the current data phase was
completed or FRAME# reasserted during the same transaction. PCI Rev 2.2- Appendix C, Rules
8b and 8d
ERR38 IRDY# was asserted during the second address phase of a Dual Address Cycle. PCI Rev 2.2- 3.9
64-bit Addressing
ERR39 TRDY# was asserted before DEVSEL# was asserted. PCI Rev 2.2- Appendix C, Rule 14
ERR40 DEVSEL#, TRDY# or STOP# were changed before the current data phase was completed, after
TRDY# was asserted. PCI Rev 2.2- Appendix C, Rule 12d
ERR41 STOP# was asserted before DEVSEL# was asserted. PCI Rev 2.2- Appendix C, Rule 14
ERR42 REQ64# was not asserted during the same time as FRAME#. PCI Rev 2.2-3.8. 64-Bit Bus
Extension
ERR43 ACK64# was not asserted during the same time as DEVSEL#.PCI Rev 2.2- 3.8. 64-Bit Bus
Extension
ERR44 REQ64# was asserted during a non-memory transaction. PCI Rev 2.2- 3.8. 64-Bit Bus Extension
ERR45 ACK64# was asserted before REQ64# was asserted. PCI Rev 2.2-3.8. 64-Bit Bus Extension
ERR46 Master abort was done prior to 4 clocks from the address phase. PCI Rev 2.2- 3.3.3.1. Master
Initiated Termination 3.9. 64-bit Addressing on PCI
ERR47 Reserved command was performed. PCI Rev 2.2- 3.1.1. Command Definition
ERR48 A second DAC was performed immediately following a DAC.PCI Rev 2.2- 3.9 64-bit Addressing
on PCI
ERR49 Byte enables were changed before the data phase was completed, A master must keep the byte
enables stable during the complete data phase. PCI Rev 2.2- Appendix C, Rule 3b
ERR50 An INTx signal has been asserted and then deasserted before an Interrupt Acknowledge. PCI Rev
2.2-3.6.4 Interrupt Acknowledge
ERR51 Bus Command was not reflected on C/BE[7..4] during DAC transaction. PCI Rev 2.2-3.9 64-bit
Addressing on PCI
ERR52 Cache signals status was changed from HITM to STANDBY, without being in a CLEAN status.
PCI Rev 2.1- 3.9.2 Cache State Transitions
ERR53 Cache signals status was changed to HITM from a non STANDBY status. PCI Rev 2.1-3.9.2
Cache State Transitions
ERR54 Data parity error was detected on AD[31..0], but PERR# was not asserted. PCI Rev 2.2-
Appendix C, Rule 37b
ERR55 Data parity error was detected on AD[63..32], but PERR# was not asserted. PCI Rev 2.2-
Appendix C, Rule 10c
ERR56 REQ# was not deasserted for a minimum of 2 clocks after a Retry and or a Disconnect by the
Target. PCI Rev 2.2- Appendix C, Rule 10
ERR57 LOCK# was not asserted the clock following the address phase or was not kept asserted
throughout the transaction. PCI Rev 2.1-Appendix C, Rule 32e
ERR58 DEVSEL#, TRDY# or STOP# were changed before the current data phase was completed, after
STOP# was asserted. PCI Rev 2.2- Appendix C, Rule 12d