Teledyne LeCroy TA660СА - Manual (Page 125)

TA660 User's Manual Catalyst Enterprises, Inc
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Table 2 Protocol Errors (0 – 58)
ERR0 DEVSEL# was removed while transaction was not completed yet. PCI Rev 2.2-3.3., Rev 2.2 -
3.3.1., 3.3.2.,
ERR1 Target does not allow for turnaround time. TRDY# asserted immediately after FRAME# in a read
transaction. PCI Rev 2.2 - 3.3.1., 3.3.2.,
ERR2 FRAME# is not asserted within 16 clocks from the time GNT# was asserted. PCI Rev 2.2 - 3.4.1.
ERR3 FRAME# is not deasserted within 3 clocks from the time STOP# was asserted. PCI Rev 2.2 -
3.3.3.2.1. Rule 5
ERR4 TRDY# is not asserted within 8 clocks on the data phase of the burst transfer. ERR4 applies only
to second or subsequent transfers, first transfer which is 16 clocks is covered by ERR7. PCI Rev
2.2 - 3.5.4.1.
ERR5 The first transaction on the LOCK# was not a read transaction. PCI Rev 2.1. - 3.6. Rule 4
ERR6 LOCK# was not released when Retry was requested by the Target. PCI Rev 2.1. - 3.6. Rule 6,
ERR7 TRDY# or STOP# not asserted within 16 clocks on the first data phase of the burst transfer. PCI
Rev 2.2. - 3.5.4.1.
ERR8 To Be Defined
ERR9 Target has not recognized configuration cycle type 00 and has asserted DEVSEL#. PCI Rev 2.2-
3.7.4.
ERR10 The IO byte address (AD0, AD1) given at the start of cycle does not match the CBE, byte enable.
PCI Rev 2.2. - 3.2.2.
ERR11 Memory Write and Invalidate Command were not implemented in Linear Incrementing Burst
Mode. PCI Rev 2.2. - 3.2.2.,
ERR12 Master Abort was done improperly. IRDY# was deasserted before TRDY# or STOP# were
asserted. PCI Rev 2.2. - 3.3.3.1. Rule 4
ERR13 STOP# was removed in the same cycle as FRAME# was removed. PCI Rev 2.2. - 3.3.3.3.2.1.
ERR14 Master did not abort within 8 clocks from the time FRAME# was asserted while DEVSEL# was
never asserted. PCI Rev 2.2. - 3.3.3.1.
ERR15 Target did not disconnect after the first phase of Reserved memory commands. PCI Rev 2.2. -
3.2.2.
ERR16 Improper termination by Target. STOP# was asserted and deasserted while FRAME# was still
asserted. PCI Rev 2.2. - 3.3.3.2.1. Rule 4
ERR17 IRDY# was not asserted within 8 clocks from the time FRAME# was asserted. PCI Rev 2.2. -
3.5.4.1.
ERR18 Target has responded to a reserved command by asserting DEVSEL#. PCI Rev 2.2. - 3.1.1.
ERR19 PERR# was asserted during special cycle. PCI Rev 2.2. - 3.7.4.1
ERR20 Back-to-Back timing was used in a transaction in which was not proceeded by a write transaction
from the same master. PCI Rev 2.2. - 3.4.2.
ERR21 PERR# was asserted during address cycle. PCI Rev 2.2. - 2.2.5.
ERR22 To Be Defined.
ERR23 FRAME# was asserted before the bus was granted (before GNT# was asserted). PCI Rev 2.2. -
3.6.3.
ERR24 IRDY# was not asserted a cycle immediately after FRAME# was deasserted. PCI Rev 2.2. -
3.3.1.
ERR25 Improper termination. Either IRDY#, TRDY#, or STOP# were not deasserted after FRAME# was
deasserted. PCI Rev 2.2. - 3.3.3.
ERR26 DEVSEL# asserted after 6 clocks from the time FRAME# was asserted. PCI Rev 2.2. - 3.3.3.1.
ERR27 Target has not deasserted TRDY# after target abort has been completed. PCI Rev 2.2. - 3.3.3.2.1.
ERR28 TRDY# asserted while target is requesting abort. PCI Rev 2.2. - 3.3.3.2.1.
ERR29 Improper Back-to-Back transaction. Either DEVSEL#, IRDY#, TRDY#, or STOP# were not
delayed and were asserted on the first cycle of the Back-to-Back transaction. PCI Rev 2.2. - 3.4.2.
ERR30 LOCK# was not released after target abort. PCI Rev 2.1. - 3.6. Rule 4