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5 stack pointer, 6 instruction execution timing – Rainbow Electronics ATtiny10 User Manual

Page 9

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9

8127B–AVR–08/09

ATtiny4/5/9/10

Figure 4-3.

The X-, Y-, and Z-registers

In different addressing modes these address registers function as automatic increment and
automatic decrement (see document “AVR Instruction Set” and section

“Instruction Set Sum-

mary” on page 151

for details).

4.5

Stack Pointer

The Stack is mainly used for storing temporary data, for storing local variables and for storing
return addresses after interrupts and subroutine calls. The Stack Pointer Register always points
to the top of the Stack. Note that the Stack is implemented as growing from higher memory loca-
tions to lower memory locations. This implies that a Stack PUSH command decreases the Stack
Pointer.

The Stack Pointer points to the data SRAM Stack area where the Subroutine and Interrupt
Stacks are located. This Stack space in the data SRAM must be defined by the program before
any subroutine calls are executed or interrupts are enabled. The Stack Pointer must be set to
point above 0x40. The Stack Pointer is decremented by one when data is pushed onto the Stack
with the PUSH instruction, and it is decremented by two when the return address is pushed onto
the Stack with subroutine call or interrupt. The Stack Pointer is incremented by one when data is
popped from the Stack with the POP instruction, and it is incremented by two when data is
popped from the Stack with return from subroutine RET or return from interrupt RETI.

The AVR Stack Pointer is implemented as two 8-bit registers in the I/O space. The number of
bits actually used is implementation dependent. Note that the data space in some implementa-
tions of the AVR architecture is so small that only SPL is needed. In this case, the SPH Register
will not be present.

4.6

Instruction Execution Timing

This section describes the general access timing concepts for instruction execution. The AVR
CPU is driven by the CPU clock clk

CPU

, directly generated from the selected clock source for the

chip. No internal clock division is used.

15

XH

XL

0

X-register

7

0

7

0

R27

R26

15

YH

YL

0

Y-register

7

0

7

0

R29

R28

15

ZH

ZL

0

Z-register

7

0

7

0

R31

R30