Rainbow Electronics ATtiny10 User Manual
Page 86
86
8127B–AVR–08/09
ATtiny4/5/9/10
switched on by setting the ADEN bit in ADCSRA. The prescaler keeps running for as long as the
ADEN bit is set, and is continuously reset when ADEN is low.
When initiating a single ended conversion by setting the ADSC bit in ADCSRA, the conversion
starts at the following rising edge of the ADC clock cycle.
A normal conversion takes 13 ADC clock cycles, as summarised in
Table 13-1 on page 87
. The
first conversion after the ADC is switched on (ADEN in ADCSRA is set) takes 25 ADC clock
cycles in order to initialize the analog circuitry. See
Figure 13-4
.
Figure 13-4. ADC Timing Diagram, First Conversion (Single Conversion Mode)
The actual sample-and-hold takes place 3 ADC clock cycles after the start of a normal conver-
sion and 16 ADC clock cycles after the start of a first conversion. See
Figure 13-5
. When a
conversion is complete, the result is written to the ADC Data Registers, and ADIF is set. In Sin-
gle Conversion mode, ADSC is cleared simultaneously. The software may then set ADSC again,
and a new conversion will be initiated on the first rising ADC clock edge.
Figure 13-5. ADC Timing Diagram, Single Conversion
When Auto Triggering is used, the prescaler is reset when the trigger event occurs. See
. This assures a fixed delay from the trigger event to the start of conversion. In this mode,
the sample-and-hold takes place two ADC clock cycles after the rising edge on the trigger
source signal. Three additional CPU clock cycles are used for synchronization logic.
Conversion Result
ADC Clock
ADSC
Sample & Hold
ADIF
ADCL
Cycle Number
ADEN
1
2
12
13
14
15
16
17
18
19
20
21
22
23
24
25
1
2
First Conversion
Next
Conversion
3
MUX
Update
MUX
Update
Conversion
Complete
1
2
3
4
5
6
7
8
9
10
11
12
13
Conversion Result
ADC Clock
ADSC
ADIF
ADCL
Cycle Number
1
2
One Conversion
Next Conversion
3
Sample & Hold
MUX
Update
Conversion
Complete
MUX
Update