1 analog comparator, 2 analog to digital converter, 3 watchdog timer – Rainbow Electronics ATtiny10 User Manual
Page 25: 4 port pins, 4 register description, 1 smcr – sleep mode control register
25
8127B–AVR–08/09
ATtiny4/5/9/10
7.3.1
Analog Comparator
When entering Idle mode, the analog comparator should be disabled if not used. In the power-
down mode, the analog comparator is automatically disabled. See
for further details.
7.3.2
Analog to Digital Converter
If enabled, the ADC will be enabled in all sleep modes. To save power, the ADC should be dis-
abled before entering any sleep mode. When the ADC is turned off and on again, the next
conversion will be an extended conversion. See
“Analog to Digital Converter” on page 83
for
details on ADC operation.
The ADC is available in ATtiny5/10, only.
7.3.3
Watchdog Timer
If the Watchdog Timer is not needed in the application, this module should be turned off. If the
Watchdog Timer is enabled, it will be enabled in all sleep modes, and hence, always consume
power. In the deeper sleep modes, this will contribute significantly to the total current consump-
tion. Refer to
for details on how to configure the Watchdog Timer.
7.3.4
Port Pins
When entering a sleep mode, all port pins should be configured to use minimum power. The
most important thing is then to ensure that no pins drive resistive loads. In sleep modes where
the I/O clock (clk
I/O
) is stopped, the input buffers of the device will be disabled. This ensures that
no power is consumed by the input logic when not needed. In some cases, the input logic is
needed for detecting wake-up conditions, and it will then be enabled. Refer to the section
Input Enable and Sleep Modes” on page 44
for details on which pins are enabled. If the input
buffer is enabled and the input signal is left floating or has an analog signal level close to V
CC
/2,
the input buffer will use excessive power.
For analog input pins, the digital input buffer should be disabled at all times. An analog signal
level close to V
CC
/2 on an input pin can cause significant current even in active mode. Digital
input buffers can be disabled by writing to the Digital Input Disable Register (DIDR0). Refer to
“DIDR0 – Digital Input Disable Register 0” on page 82
for details.
7.4
Register Description
7.4.1
SMCR – Sleep Mode Control Register
The SMCR Control Register contains control bits for power management.
• Bits 7:4 – Res: Reserved Bits
These bits are reserved and will always read zero.
Bit
7
6
5
4
3
2
1
0
0x3A
–
–
–
–
SM2
SM1
SM0
SE
SMCR
Read/Write
R
R
R
R
R/W
R/W
R/W
R/W
Initial Value
0
0
0
0
0
0
0
0