Rainbow Electronics ATtiny10 - Manual (Page 85)

85
8127B–AVR–08/09
ATtiny4/5/9/10
Figure 13-2. ADC Auto Trigger Logic
Using the ADC interrupt flag as a trigger source makes the ADC start a new conversion as soon
as the ongoing conversion has finished. The ADC then operates in Free Running mode, con-
stantly sampling and updating the ADC data register. The first conversion must be started by
writing a logical one to bit ADSC bit in ADCSRA. In this mode the ADC will perform successive
conversions independently of whether the ADC Interrupt Flag, ADIF is cleared or not.
If Auto Triggering is enabled, single conversions can be started by writing ADSC in ADCSRA to
one. ADSC can also be used to determine if a conversion is in progress. The ADSC bit will be
read as one during a conversion, independently of how the conversion was started.
13.5 Prescaling and Conversion Timing
By default, the successive approximation circuitry requires an input clock frequency between 50
kHz and 200 kHz to get maximum resolution.
Figure 13-3. ADC Prescaler
The ADC module contains a prescaler, as illustrated in Figure 13-3 on page 85 , which generates
an acceptable ADC clock frequency from any CPU frequency above 100 kHz. The prescaling is
set by the ADPS bits in ADCSRA. The prescaler starts counting from the moment the ADC is
ADSC
ADIF
SOURCE 1
SOURCE n
ADTS[2:0]
CONVERSION
LOGIC
PRESCALER
START CLK
ADC
.
.
.
.
EDGE
DETECTOR
ADATE
7-BIT ADC PRESCALER
ADC CLOCK SOURCE
CK
ADPS0
ADPS1
ADPS2
CK/128 CK/2 CK/4 CK/8 CK/16 CK/32 CK/64
Reset
ADEN
START