Rainbow Electronics ATtiny10 - Manual (Page 81)

81
8127B–AVR–08/09
ATtiny4/5/9/10
12. Analog Comparator
The Analog Comparator compares the input values on the positive pin AIN0 and negative pin
AIN1. When the voltage on the positive pin AIN0 is higher than the voltage on the negative pin
AIN1, the Analog Comparator output, ACO, is set. The comparator can trigger a separate inter-
rupt, exclusive to the Analog Comparator. The user can select Interrupt triggering on comparator
output rise, fall or toggle. A block diagram of the comparator and its surrounding logic is shown
in
Figure 12-1 .
Figure 12-1. Analog Comparator Block Diagram.
See Figure 1-1 on page 2 for pin use of analog comparator, and Table 10-4 on page 49 and
Table 10-5 on page 50 for alternate pin usage.
12.1 Register Description
12.1.1 ACSR – Analog Comparator Control and Status Register
• Bit 7 – ACD: Analog Comparator Disable
When this bit is written logic one, the power to the analog comparator is switched off. This bit
can be set at any time to turn off the analog comparator, thus reducing power consumption in
Active and Idle mode. When changing the ACD bit, the analog comparator Interrupt must be dis-
abled by clearing the ACIE bit in ACSR. Otherwise an interrupt can occur when the bit is
changed.
• Bits 6 – Res: Reserved Bit
This bit is reserved and will always read zero.
• Bit 5 – ACO: Analog Comparator Output
Enables output of analog comparator. The output of the analog comparator is synchronized and
then directly connected to ACO. The synchronization introduces a delay of 1 - 2 clock cycles.
Bit 7 6 5 4 3 2 1 0
0x1F ACD – ACO ACI ACIE ACIC ACIS1 ACIS0 ACSR
Read/Write R/W R R R/W R/W R/W R/W R/W
Initial Value 0 0 0 0 0 0 0 0