Rainbow Electronics ATtiny10 - Manual (Page 56)

56
8127B–AVR–08/09
ATtiny4/5/9/10
Figure 11-4. Counter Unit Block Diagram
Signal description (internal signals):
Count Increment or decrement TCNT0 by 1.
Direction Select between increment and decrement.
Clear Clear TCNT0 (set all bits to zero).
clk
T 0
Timer/Counter clock.
TOP Signalize that TCNT0 has reached maximum value.
BOTTOM Signalize that TCNT0 has reached minimum value (zero).
The 16-bit counter is mapped into two 8-bit I/O memory locations: Counter High (TCNT0H) con-
taining the upper eight bits of the counter, and Counter Low (TCNT0L) containing the lower eight
bits. The TCNT0H Register can only be indirectly accessed by the CPU. When the CPU does an
access to the TCNT0H I/O location, the CPU accesses the high byte temporary register (TEMP).
The temporary register is updated with the TCNT0H value when the TCNT0L is read, and
TCNT0H is updated with the temporary register value when TCNT0L is written. This allows the
CPU to read or write the entire 16-bit counter value within one clock cycle via the 8-bit data bus.
It is important to notice that there are special cases of writing to the TCNT0 Register when the
counter is counting that will give unpredictable results. The special cases are described in the
sections where they are of importance.
Depending on the mode of operation used, the counter is cleared, incremented, or decremented
at each timer clock (clk
T 0
). The clk
T 0
can be generated from an external or internal clock source,
selected by the Clock Select bits (CS02:0). When no clock source is selected (CS02:0 = 0) the
timer is stopped. However, the TCNT0 value can be accessed by the CPU, independent of
whether clk
T 0
is present or not. A CPU write overrides (has priority over) all counter clear or
count operations.
The counting sequence is determined by the setting of the Waveform Generation mode bits
(WGM03:0) located in the Timer/Counter Control Registers A and B (TCCR0A and TCCR0B).
There are close connections between how the counter behaves (counts) and how waveforms
are generated on the Output Compare outputs OC0x. For more details about advanced counting
sequences and waveform generation, see
“Modes of Operation” on page 62 .
The Timer/Counter Overflow Flag (TOV0) is set according to the mode of operation selected by
the WGM03:0 bits. TOV0 can be used for generating a CPU interrupt.
TEMP (8-bit)
DATA BUS
(8-bit)
TCNTn (16-bit Counter)
TCNTnH (8-bit) TCNTnL (8-bit)
Control Logic
Count
Clear
Direction
TOVn
(Int.Req.)
Clock Select
TOP BOTTOM
Tn
Edge
Detector
( From Prescaler )
clk
Tn