Rainbow Electronics ATtiny10 - Manual (Page 84)

84
8127B–AVR–08/09
ATtiny4/5/9/10
Figure 13-1. Analog to Digital Converter Block Schematic
13.4 Starting a Conversion
Make sure the ADC is powered by clearing the ADC Power Reduction bit, PRADC, in the Power
Reduction Register, PRR (see
“PRR – Power Reduction Register” on page 26 ).
A single conversion is started by writing a logical one to the ADC Start Conversion bit, ADSC.
This bit stays high as long as the conversion is in progress and will be cleared by hardware
when the conversion is completed. If a different data channel is selected while a conversion is in
progress, the ADC will finish the current conversion before performing the channel change.
Alternatively, a conversion can be triggered automatically by various sources. Auto Triggering is
enabled by setting the ADC Auto Trigger Enable bit, ADATE in ADCSRA. The trigger source is
selected by setting the ADC Trigger Select bits, ADTS in “ADCSRB – ADC Control and Status
Register B”. See
Table 13-4 on page 95 for a list of the trigger sources. When a positive edge
occurs on the selected trigger signal, the ADC prescaler is reset and a conversion is started.
This provides a method of starting conversions at fixed intervals. If the trigger signal still is set
when the conversion completes, a new conversion will not be started. If another positive edge
occurs on the trigger signal during conversion, the edge will be ignored. Note that an interrupt
flag will be set even if the specific interrupt is disabled. A conversion can thus be triggered with-
out causing an interrupt. However, the interrupt flag must be cleared in order to trigger a new
conversion at the next interrupt event.
ADMUX
DECODER
8-BIT DATA BUS
MUX1 MUX0
ADCSRA ADCL
ADPS0
ADEN
ADPS1 ADPS2 AD
A
T
E
ADIF
ADSC
TRIGGER
SELECT
VREF
ADTS2:0
ST
AR
T
PRESCALER
ADC7:0
CONVERSION LOGIC
8-BIT DAC
ADCSRB
-
+ ADC3
ADC2
ADC1
ADC0
V
CC
INPUT
MUX
INTERR
UPT FLA
GS
ADIE
ADC IRQ
SAMPLE & HOLD
COMPARATOR
CHANNEL