Rainbow Electronics ATtiny10 - Manual (Page 87)

87
8127B–AVR–08/09
ATtiny4/5/9/10
Figure 13-6. ADC Timing Diagram, Auto Triggered Conversion
In Free Running mode (see Figure 13-7 ), a new conversion will be started immediately after the
conversion completes, while ADSC remains high.
Figure 13-7. ADC Timing Diagram, Free Running Conversion
For a summary of conversion times, see Table 13-1 .
Table 13-1. ADC Conversion Time
Condition
Sample & Hold (Cycles from
Start of Conversion) Conversion Time (Cycles)
First conversion 16.5 25
Normal conversions 3.5 13
Auto Triggered conversions 4 13.5
1 2 3 4 5 6 7 8 9 10 11 12 13
Conversion Result
ADC Clock
Trigger
Source
ADIF
ADCL
Cycle Number 1 2
One Conversion Next Conversion
Conversion
Complete
Prescaler
Reset
ADATE
Prescaler
Reset
Sample &
Hold
MUX
Update
11 12 13
Conversion Result
ADC Clock
ADSC
ADIF
ADCL
Cycle Number
1 2
One Conversion Next Conversion
3 4
Conversion complete Sample & Hold
MUX update