Texas Instruments TMS320C3x - Manual (Page 755)

Index
Index-14
repeat end-address (RE) register 3-17, 7-2
repeat mode, definition D-6
repeat modes 7-2–7-8
control algorithm 7-4
control bits 7-3
maximum number of repeats 7-3
nested block repeats 7-8
operation 7-3–7-4
RC register value 7-7
restrictions 7-6–7-7
RPTB instruction 7-4–7-5
RPTS instruction 7-5
repeat start-address (RS) register 3-17, 7-2
repeat-counter (RC) register 3-17, 7-2
definition D-6
reset 4-14
definition D-6
operation 7-21–7-25
performed 7-25
pin states 7-21
reset and interrupt vector priorities 7-31
reset pin, definition D-6
reset, interrupt, and trap vector, locations, micropro-
cessor mode, TMS320C31 4-16
reset/interrupt,/trap vector, locations, microproces-
sor mode, TMS320C30 and TMS320C31 7-27
reset/interrupt/trap vector
locations
microcomputer boot mode,
TMS320C31 7-28
microprocessor mode, TMS320C30 4-15
map
microcomputer mode 4-14
microcomputer/boot-loader mode 4-14
microprocessor and microcomputer/boot-load-
er mode 4-14
microprocessor mode 4-14
restore clock to regular speed instruction
(MAXSPEED) 13-145
RETIcond instruction 7-48
return
from interrupt conditionally instruction (RETI-
cond) 7-12, 13-198
from subroutine 7-11
from subroutine conditionally (RETS-
cond) 13-200
from subroutine conditionally instruction (RETS-
cond) 7-11
RND instruction 5-39
flowchart 5-40
ROM. See memory
rotate
left instruction (ROL) 13-204
left through carry (ROLC) 13-205
right instruction (ROR) 13-207
right through carry instruction (RORC) 13-208
rotating priority, for ’C32 12-63
round floating-point value instruction
(RND) 13-202
rounding of floating-point value 5-39–5-40
RPTB instruction 7-4–7-5
nesting 7-8
pipeline conflict in 7-7
to flush pipeline 8-5
RPTS instruction 7-5–7-6
to flush pipeline 8-5
S
segment start address (SSA) 4-19
semaphores, using in critical sections 7-17
serial port 12-15–12-47
block diagram 12-16
clock 12-15, 12-31
configurations 12-29–12-31
timer 12-42
timing 12-31–12-34
continuous transmit and receive mode 12-33
CPU transfer with transmit polling 12-43–12-44
data-receive register 12-28–12-29
data-transmit register 12-28
fixed data-rate timing 12-36
burst mode 12-36
continuous mode 12-36
frame sync 12-37, 12-38
functional operation 12-35–12-41
global-control register 12-15, 12-17–12-21
handshake mode 12-19, 12-33–12-35, 12-42,
12-43
direct connect
12-34
initialization reconfiguration 12-41–12-47
interface examples
handshake mode example 12-42–12-43
serial A/C interface example 12-45
serial A/D and DIA interface exam-
ple 12-46–12-48
interrupt sources 12-34