Texas Instruments TMS320C3x User Manual
Page 748

Index
Index-7
extended-precision
(R7–R0) registers
definition
floating-point format, definition
external
buses (expansion, primary)
interface
control registers
memory map
timing, expansion bus I/O cycles
timing, primary bus cycles
interrupt
buses (expansion, primary)
definition
interlocked-instruction signaling
memory interface
configurations
control registers
features
overview
timing
reset signal
external bus operation
external interface control registers
expansion bus
primary bus
external interface timing
expansion-bus I/O cycles
primary-bus cycles
external memory interface timing, expansion
bus
programmable
bank switching
wait states
F
FFT algorithms, using bit-reversed addressing to
implement
FIFO buffer, definition
FIR filters, implementation using circular addres-
sing
FIX instruction
flowchart
fixed data-rate timing operation
burst-mode timing
continuous-mode timing
fixed priority, for ’C32
flag
carry
condition
floating-point underflow
latched floating-point underflow
latched overflow
negative
overflow
zero
FLOAT instruction, flowchart
floating-point
addition, flowchart
multiplication
examples
flowchart
operation
to integer conversion instruction (FIX)
underflow condition flag
values
fractional
negative
positive
floating-point format
2s-complement, converting IEEE format to
addition and subtraction
examples
conversion
between formats
TMS320C3x to IEEE
to IEEE standard 754, 5-14
to integer
converting integer to
determining decimal equivalent
extended-precision
normalization
rounding value
multiplication
short, for external 16-bit data, TMS320C32
single-precision
frame sync
FSX pins
G
general addressing modes
global memory, sharing
by multiple processors