Texas Instruments TMS320C3x - Manual (Page 346)

Bus Timing
10-43 TMS320C32 Enhanced External Memory Interface
Figure 10–27 illustrates a zero wait-state read and write sequence for IOSTRB
active. During writes, the data is valid when IOSTRB changes.
Figure 10–27. Zero Wait-State Read and Write Sequence for IOSTRB Active
Write Read
IOSTRB
RDY
D
A
R/W
H1
H3
Figure 10–28 depicts a one wait-state read sequence for IOSTRB active.
Figure 10–29 shows a one wait-state write sequence for IOSTRB active. For
each wait-state added, IOSTRB, R/W, and A are extended for one extra clock
cycle. Writes hold the data on the bus for one extra clock cycle. RDY is sampled
on each extra cycle and the sequence is terminated when RDY is low.