Texas Instruments TMS320C3x - Manual (Page 560)

FIX||STI Parallell FIX and STI
13-102
Status Bits These condition flags are modified only if the destination register is R7 – R0.
LUF Unaffected
LV 1 if an integer overflow occurs; unchanged otherwise
UF 0
N 1 if a negative result is generated; 0 otherwise
Z 1 if a 0 result is generated; 0 otherwise
V 1 if an integer overflow occurs; 0 otherwise
C Unaffected
OVM Operation is not affected by OVM bit value.
Example FIX *++AR4(1),R1
|| STI R0,*AR2
Before Instruction After Instruction
R0 00 0000 00DC R0 00 0000 00DC
R1 00 0000 0000 R1 00 0000 00B3
AR2 80 983C AR2 80 983C
AR4 80 98A2 AR4 80 98A3
LUF 0 LUF 0
LV 0 LV 0
UF 0 UF 0
N 0 N 0
Z 0 Z 0
V 0 V 0
C 0 C 0
Data memory
8098A3h 733C000 8098A3 733C000
80983Ch 0 80983C 0DC
220
1.7950e+02
220
179
1.79750e+02
220
Note: Cycle Count
See Section 8.5.2, Data Loads and Stores, on page 8-24 for the effects of
operand ordering on the cycle count.
Mode Bit