Texas Instruments TMS320C3x - Manual (Page 209)

Reset Operation
7-25 Program Flow Control
At system reset, the following additional operations are performed:
- The peripherals are reset. This is a synchronous operation. Peripheral reset
is described in Chapter 12,
Peripherals.
- The external bus control registers are reset. The reset values of the control
registers are described in Chapter 9,
’C30 and ’C31 External-Memory
Interface.
- The following CPU registers are loaded with 0:
J ST (CPU status register), except in the ’C32, the PRGW status bit field
is loaded with the status of the PRGW pin
J IE (CPU/DMA interrupt-enable flags)
J IF (CPU interrupt flags)
J IOF (I/O flags)
- The reset vector is read from memory location 0h. On the ’C32, this is a
32-bit data read. Once read, this value is loaded into the PC. This vector
contains the start address of the system reset routine.
- At this point, code location is dictated by the PC.
Multiple ’C3x devices, driven by the same system clock, may be reset and
synchronized. When the 1 to 0 transition of RESET occurs, the processor is
placed on a well-defined internal phase, and all of the ’C3x devices come up
on the same internal phase and all internal memory locations.
Unless otherwise specified, all registers are undefined after reset.