Texas Instruments TMS320C3x - Manual (Page 703)

Test Bit Fields TSTB
13-245 Assembly Language Instructions
Syntax TSTB src, dst
Operation dst AND src
Operands src general addressing modes (G):
0 0 register (R n, 0
≤
n
≤
27)
0 1 direct
1 0 indirect (disp = 0–255, IR0, IR1)
1 1 immediate
dst register (Rn, 0
≤
n
≤
27)
Opcode
31 24 23 16 8 7 0 15
0 0 0 1 1 0 1 0 0 dst G src
Description The bitwise-logical AND of the dst and src operands is formed, but the result
is not loaded in any register. This allows for nondestructive compares. The dst
and src operands are assumed to be unsigned integers.
Cycles 1
Status Bits These condition flags are modified for all destination registers (R27 – R0).
LUF Unaffected
LV Unaffected
UF 0
N MSB of the output
Z 1 if a 0 output is generated; 0 otherwise
V 0
C Unaffected
OVM Operation is not affected by OVM bit value. Mode Bit