Texas Instruments TMS320C3x - Manual (Page 354)

Bus Timing
10-51 TMS320C32 Enhanced External Memory Interface
Figure 10–40. IOSTRB Read and Read
I/O Read I/O Read
IOSTRB
RDY
D
A
R/W
H1
H3
10.10.3 Inactive Bus States
Figure 10–41 and Figure 10–42 show the signal states when a bus becomes
inactive after an IOSTRB or STRBx, respectively. The strobes (STRB0,
STRB1, IOSTRB, and R / W) are deasserted going to a high level. The address
bus preserves the last value and the ready signal (RDY) is ignored.
Figure 10–41. Inactive Bus States Following IOSTRB Bus Cycle
I/O Write
IOSTRB
RDY
D
A
R/W
H1
H3
Bus inactive RDY ignored