Texas Instruments TMS320C3x User Manual

Page 717

background image

Instruction Opcodes

A-6

Table A–1. TMS320C3x Instruction Opcodes (Continued)

Instruction

23

24

25

26

27

28

29

30

31

ABSI||STI

1

1

0

0

1

0

1

–

–

ADDF3||STF

1

1

0

0

1

1

0

–

–

ADDI3||STI

1

1

0

0

1

1

1

–

–

AND3||STI

1

1

0

1

0

0

0

–

–

ASH3||STI

1

1

0

1

0

0

1

–

–

FIX||STI

1

1

0

1

0

1

0

–

–

FLOAT||STF

1

1

0

1

0

1

1

–

–

LDF||STF

1

1

0

1

1

0

0

–

–

LDI||STI

1

1

0

1

1

0

1

–

–

LSH3||STI

1

1

0

1

1

1

0

–

–

MPYF3||STF

1

1

0

1

1

1

1

–

–

MPYI3||STI

1

1

1

0

0

0

0

–

–

NEGF||STF

1

1

1

0

0

0

1

–

–

NEGI||STI

1

1

1

0

0

1

0

–

–

NOT||STI

1

1

1

0

0

1

1

–

–

OR3||STI

1

1

1

0

1

0

0

–

–

SUBF3||STF

1

1

1

0

1

0

1

–

–

SUBI3||STI

1

1

1

0

1

1

0

–

–

XOR3||STI

1

1

1

0

1

1

1

–

–

Reserved for reset,
traps, and interrupts

0

1

1

1

1

1

1

1

1

† The opcode is the same for standard and delayed instructions.