Texas Instruments TMS320C3x - Manual (Page 528)

ANDN3 Bitwise-Logical ANDN, 3-Operand
13-70
Example 1 ANDN3 R5,R3,R7
Before Instruction After Instruction
R3 00 0000 0C2F R3 00 0000 0C2F
R5 00 0000 0A02 R5 00 0000 0A02
R7 00 0000 0000 R7 00 0000 042D
LUF 0 LUF 0
LV 0 LV 0
UF 0 UF 0
N 0 N 0
Z 0 Z 0
V 0 V 0
C 0 C 0
Example 2 ANDN3 R1,*AR5++(IR0),R0
Before Instruction After Instruction
R0 00 0000 0000 R0 00 0000 0F30
R1 00 0000 00CF R1 00 0000 00CF
AR5 80 9825 AR5 80 982A
IR0 5 IR0 5
LUF 0 LUF 0
LV 0 LV 0
UF 0 UF 0
N 0 N 0
Z 0 Z 0
V 0 V 0
C 0 C 0
Data memory
809825h 0FFF 809825h 0FFF
Note: Cycle Count
See Section 8.5.2, Data Loads and Stores, on page 8-24 for the effects of
operand ordering on the cycle count.