Texas Instruments TMS320C3x - Manual (Page 206)

Reset Operation
7-22
Table 7–3. TMS320C3x Pin Operation at Reset (Continued)
Device
Signal ‘C32 ‘C31 ‘C30 Operation at Reset
HOLDA Reset has no effect n n n
PRGW Reset has no effect
n
Expansion Bus Interface
XD31 – XD0 Synchronous reset; placed in high-impedance state n
XA12 – XA0 Synchronous reset; placed in high-impedance state n
XR/W Synchronous reset; placed in high-impedance state n
MSTRB Synchronous reset; deasserted by going to a high level n
XRDY Reset has no effect n
Control Signals
RESET Reset input pin
n n n
INT3 – INT0 Reset has no effect
n n n
IACK Synchronous reset; deasserted by going to a high level n n n
MC/MP or MCBL/MP Reset has no effect n n n
SHZ Reset has no effect n n n
XF1–XF0 Asynchronous reset; placed in high-impedance state n n n
Serial Port 0 Signals
CLKX0 Asynchronous reset; placed in high-impedance state n n n
DX0 Asynchronous reset; placed in high-impedance state n n n
FSX0 Asynchronous reset; placed in high-impedance state
n n n
CLKR0 Asynchronous reset; placed in high-impedance state
n n n
DR0 Asynchronous reset; placed in high-impedance state n n n
FSR0 Asynchronous reset; placed in high-impedance state n n n
Serial Port 1 Signals
CLKX1 Asynchronous reset; placed in high-impedance state n
DX1 Asynchronous reset; placed in high-impedance state n
FSX1 Asynchronous reset; placed in high-impedance state n
CLKR1 Asynchronous reset; placed in high-impedance state
n