Texas Instruments TMS320C3x - Manual (Page 678)

STII Store Integer, Interlocked
13-220
Syntax STII src, dst
Operation src
→
dst
Signal end of interlocked operation
Operands src register (Rn, 0
≤
n
≤
27)
dst general addressing modes (G):
0 1 direct
1 0 indirect (disp = 0–255, IR0, IR1)
Opcode
31 24 23 16 8 7 0 15
0 0 0 1 0 1 0 1 1 src G dst
Description The src register is loaded into the dst memory location. An interlocked opera-
tion is signaled over pins XF0 and XF1. The src and dst operands are assumed
to be signed integers. Refer to Section 7.4, Interlocked Operations, on page
7-13 for detailed information.
Cycles 1
Status Bits LUF Unaffected
LV Unaffected
UF Unaffected
N Unaffected
Z Unaffected
V Unaffected
C Unaffected
OVM Operation is not affected by OVM bit value.
Example STII R1,@98AEh
Before Instruction After Instruction
R1 00 0000 078D R1 00 0000 078D
DP 080 DP 080
Data memory
8098AEh 25C 8098AEh 78D
Note:
The STII instruction is not interruptible because it completes when ready is
signaled. See Section 7.4,
Interlocked Operations, on page 7-13.
Mode Bit