Texas Instruments TMS320C3x - Manual (Page 286)

External Memory Interface Timing
9-20
Figure 9–9 illustrates a write cycle with one wait state. Since initially (X)RDY = 1,
the write cycle is extended. (M)STRB, (X)R/W, and (X)A are extended one cycle.
The next time (X)RDY is sampled, it is 0.
Figure 9–9. Use of Wait States for Write for (M)STRB = 0
H3
H1
(X)A
(X)D
(X)RDY
(M)STRB
(X)R/W
Write data Write data
Extra
cycle