Texas Instruments TMS320C3x - Manual (Page 207)

Reset Operation
7-23 Program Flow Control
Table 7–3. TMS320C3x Pin Operation at Reset (Continued)
Device
Signal ‘C32 ‘C31 ‘C30 Operation at Reset
DR1 Asynchronous reset; placed in high-impedance state n
FSR1 Asynchronous reset; placed in high-impedance state n
Timer0 Signal
TCLK0 Asynchronous reset; placed in high-impedance state n n n
Timer1 Signal
TCLK1 Asynchronous reset; placed in high-impedance state n n n
Supply and Oscillator Signals
V
DD
Reset has no effect n n n
IODV
DD
Reset has no effect
n
ADV
DD
Reset has no effect
n
PDV
DD
Reset has no effect n
DDV
DD
Reset has no effect n
MDV
DD
Reset has no effect n
V
SS
Reset has no effect
n n n
DV
SS
Reset has no effect
n n
CV
SS
Reset has no effect n n
IV
SS
Reset has no effect n n
V
BBP
Reset has no effect n n
V
SUBS
Reset has no effect
n n n
X1 Reset has no effect n n
X2/CLKIN Reset has no effect n n n
H1 Synchronous reset; will go to its initial state when RESET
makes a 1 to 0 transition n n n
H3 Synchronous reset; will go to its initial state when RESET
makes a 1 to 0 transition n n n