Texas Instruments TMS320C3x - Manual (Page 749)

Index
Index-8
global-control register
DMA 12-53–12-59
serial port 12-15, 12-17–12-21
timer 12-3, 12-4–12-6
H
handshake 11-20
hardware interrupt, definition D-3
hit, definition D-3
hold cycles 9-37
hold everything 8-15
busy external port 8-16
conditional calls and traps 8-18
multicycle data reads 8-17
I
I/O flag (IOF) register 3-16
bits defined 3-16
CPU register file 3-16
definition D-4
I/O flags, external 2-21
IACK instruction 7-35
IACK signal, definition D-4
idle until interrupt instruction (IDLE) 13-109
IDLE2
interrupt response timing 7-51
power-down mode 7-49–7-51
timing 7-50
IEEE format, converting floating-point format
to 5-21
IIOF flag register (IIF), definition D-2
immediate addressing 6-18–6-29
inactive bus states 10-51
index registers
(IR1, IR0) 3-4
definition D-4
indirect addressing 6-5–6-29
3-operand addressing mode 13-25
ARAUs 6-5
auxiliary register 6-5
parallel addressing mode 13-26
with postdisplacement 6-11
with postinde
6-15–6-18
with predisplacement 6-9–6-11
indirect addressing (continued)
with preinde 6-13–6-15
instruction
2-operand 13-3
3-operand 13-4
cache 4-19
algorithm 4-21
TMS320C32 2-16
CALL 7-11
CALLcond 7-11
DBR 8-8
FIX 5-41
FLOAT 5-43
IACK 7-35
IDLE2 7-49
interlocked operations 13-5–13-6
ISR 7-35
LDFI 7-14
LDII 7-14
load and store 13-2
low-power control operations 13-5
LOWPOWER 7-51
NOP 7-45
NORM 5-37
POP ST 7-41
program control 13-4–13-5
PUSH ST 7-41
RETIcond 7-12, 7-48
RETScond 7-11
RND 5-39
RPTB 7-2, 7-4
RPTS 7-2, 7-5
SIGI 7-14
STFI 7-14
STII 7-14
TRAPcond 7-11
instruction register (IR) 2-18
instruction register (IR) 3-18
instruction set 13-38–13-172
example instruction 13-38–13-40
summary, table 13-10
integer format 5-2
short integer 5-2
sign-extended 5-2
single-precision 5-2
unsigned 5-3
integer to floating-point conversion
instruction (FLOAT) 13-103
using the FLOAT instruction 5-43