Texas Instruments TMS320C3x - Manual (Page 72)

CPU Multiport Register File
3-9 CPU Registers
3.1.8 CPU/DMA Interrupt-Enable (IE) Register
The CPU/DMA interrupt-enable (IE) register of the ’C30, ’C31, and ’C32 are
32-bit registers (see Figure 3–5 and Figure 3–6). The CPU interrupt-enable bits
are in locations 10–0 for ’C30 and ’C31 devices, and 11–0 for ’C32 devices. The
direct memory access (DMA) interrupt-enable bits are in locations 26–16 for
‘C30 and ‘C31 devices, and 31–16 for ’C32 devices. A 1 in a CPU/DMA IE bit
enables the corresponding interrupt. A 0 disables the corresponding interrupt.
At reset, 0 is written to this register.
Table 3–3 describes the interrupt-enable register bits, their names, and their
functions.
Figure 3–5. CPU/DMA Interrupt-Enable (IE) Register
(TMS320C30 and TMS320C31)
xx
31
xx
30
xx
29
xx
28
xx
27
EDINT
(DMA)
26
R/W
ETINT1
(DMA)
25
R/W
ETINT0
(DMA)
24
R/W
ERINT1
(DMA)
23
R/W
EXINT1
(DMA)
22
R/W
ERINT0
(DMA)
21
R/W
EXINT0
(DMA)
20
R/W
EINT3
(DMA)
19
R/W
EINT2
(DMA)
18
R/W
EINT1
(DMA)
17
R/W
EINT0
(DMA)
16
R/W
xx
15
xx
14
xx
13
xx
12
xx
EDINT
(CPU)
10
R/W
ETINT1
(CPU)
9
R/W
ETINT0
(CPU)
8
R/W
ERINT1
(CPU)
7
R/W
EXINT1
(CPU)
6
R/W
ERINT0
(CPU)
5
R/W
EXINT0
(CPU)
4
R/W
EINT3
(CPU)
3
R/W
EINT2
(CPU)
2
R/W
EINT1
(CPU)
1
R/W
EINT0
(CPU)
0
R/W
11
Notes: 1) xx = reserved bit, read as 0
2) R = read, W = write
Figure 3–6. CPU/DMA Interrupt-Enable (IE) Register (TMS320C32)
EINT1
(DMA0)
16
EINT0
(DMA0)
31 30 29 28
EDINT1
(DMA0)
26
R/W
ETINT1
(DMA0)
25
R/W
ETINT0
(DMA0)
24
R/W
ETINT1
(DMA1)
23
R/W
ETINT0
(DMA1)
22
R/W
ERINT0
(DMA1)
21
R/W
EXINT0
(DMA0)
20
R/W
EINT3
(DMA0)
19
R/W
EINT2
(DMA0)
18
R/W
17
R/W R/W
EDINT0
(DMA1)
27
R/W
EINT0
(DMA1)
R/W
EINT1
(DMA1)
R/W
EINT2
(DMA1)
R/W
EINT3
(DMA1)
R/W
xx
15
xx
14
xx
13
xx
12
EDINT0
(CPU)
10
R/W
ETINT1
(CPU)
9
R/W
ETINT0
(CPU)
8
R/W
xx
7
xx
6
R/W
ERINT0
(CPU)
5
R/W
EXINT0
(CPU)
4
R/W
EINT3
(CPU)
3
R/W
EINT2
(CPU)
2
R/W
EINT1
(CPU)
1
R/W
EINT0
(CPU)
0
R/W
11
EDINT1
(CPU)
R/W
Notes: 1) xx = reserved bit, read as 0
2) R = read, W = write