Texas Instruments TMS320C3x - Manual (Page 344)

Bus Timing
10-41 TMS320C32 Enhanced External Memory Interface
Figure 10–25 shows a one wait-state read sequence and Figure 10–26 shows
the write sequence for STRBx active. On the first H1 cycle, RDY is high; therefore,
the read or write sequence is extended for one extra cycle. On the second H1
cycle, RDY is low and the read or write sequence is terminated.
Figure 10–25. One Wait-State Read Sequence for STRBx Active
STRBx
RDY
D
A
R/W
H1
H3
Extra cycle
Read