Texas Instruments TMS320C3x User Manual
Page 751
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Index
Index-10
logical shift instruction (LSH)
LOPOWER
timing
low-power
control instructions
idle instruction (IDLE2)
LRU cache update
LSB, definition
M
mantissa, definition
maskable interrupt, definition
MAXSPEED, timing
memory
accesses
2-operand instructions
3-operand instructions
data access
data loads and stores
internal clock
pipeline
program fetch
timing
two data accesses
addressing modes
cache
configured, TMS320C31, byte-wide
conflicts
execute only
hold everything
program fetch incomplete
program wait
data, TMS320C32
DMA memory transfer
enhanced interface, TMS320C32
general organization
global, sharing
by multiple processors
interface
16-bit wide
32-bit wide
8-bit wide
control registers
signals
maps
peripheral bus
TMS320C30
TMS320C31
memory (continued)
TMS320C32
TMS320C30
TMS320C31
microcomputer mode
TMS320C30
TMS320C31
TMS320C32
microprocessor mode
TMS320C30
TMS320C31
TMS320C32
organization, block diagram
TMS320C30
TMS320C31
TMS320C32
parallel
multiplies and adds
stores
pipeline conflicts
program, TMS320C32
timing
TMS320C31, configured
16-bit-wide
32-bit-wide
widths
16-bit with 16-bit data type size
16-bit with 32-bit data type size
16-bit with 8-bit data type size
32-bit with 16-bit data type size
32-bit with 32-bit data type size
32-bit with 8-bit data type size
8-bit with 16-bit data type size
8-bit with 32-bit data type size
8-bit with 8-bit data type size
memory-mapped register, definition
MFLOPS, definition
microcomputer mode, definition
microprocessor mode, definition
MIPS, definition
miss, definition
modes, boot loader
flowchart
TMS320C31
TMS320C32
mode selection
TMS320C31
TMS320C32