Texas Instruments TMS320C3x - Manual (Page 74)

CPU Multiport Register File
3-11 CPU Registers
Table 3–3. IE Bits and Functions(Continued)
Abbreviation Description
Reset
Value
ETINT0 (DMA) 0 DMA timer0 interrupt enable (’C30 and ’C31)
ETINT1 (DMA) 0 DMA timer1 interrupt enable (’C30 and ’C31 only)
ETINT0 (DMA0) 0 DMA0 timer1 interrupt enable (’C32 only)
ETINT1 (DMA0) 0 DMA0 timer1 interrupt enable (’C32 only)
ETINT0 (DMA1) 0 DMA1 timer0 interrupt enable (’C32 only)
ETINT1 (DMA1) 0 DMA1 timer1 interrupt enable (’C32 only)
EDINT (DMA) 0 DMA controller interrupt enable (’C30 and ’C31 only)
EDINT1 (DMA0) 0 DMA0-DMA1 controller interrupt enable (’C32 only)
EDINT0 (DMA1) 0 DMA1-DMA0 controller interrupt enable (’C32 only)
EINT0 (DMA1) 0 DMA1 external interrupt 0 enable (’C32 only)
EINT1 (DMA1) 0 DMA1 external interrupt 1 enable (’C32 only)
EINT2 (DMA1) 0 DMA1 external interrupt 2 enable (’C32 only)
EINT3 (DMA1) 0 DMA1 external interrupt 2 enable (’C32 only)
3.1.9 CPU Interrupt Flag (IF) Register
Figure 3–7, Figure 3–8, and Figure 3–9 show the 32-bit CPU interrupt flag reg-
isters (IF) for the ‘C30, ‘C31, and ‘C32 devices, respectively. A 1 in a CPU IF
register bit indicates that the corresponding interrupt is set. The IF bits are set
to 1 when an interrupt occurs. They may also be set to 1 through software to
cause an interrupt. A 0 indicates that the corresponding interrupt is not set. If
a 0 is written to an IF register bit, the corresponding interrupt is cleared. At reset,
0 is written to this register. Table 3–4 describes the interrupt flag register bits,
their names, and their functions.