Texas Instruments TMS320C3x - Manual (Page 449)

DMA
Controller
12-70
Figure 12–48. DMA Timing When Destination is an STRB, STRB0, STRB1, MSTRB Bus
Cycles
(H1)
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 Rate
Source
on chip
R1 R2 R3 R4 R5
Destination
STRB,
STRB0,
W1 W1 W1 W1 W2 W2 W2 W2 W3 W3 W3 W3 W4 W4 W4 W4 . . .
(1 + 2 + C w) T
STRB1,
MSTRB
bus
Cw Cw Cw Cw
Source
STRB,
STRB0
R1 R1 R1 I R2 R2 R2 I
{
STRB0,
STRB1
bus
Cr Cr
(2 + C r + 2 + C w) T + 0.5 ( T – 1)
{
Destination
STRB, W1 W1 W1 W1 W2 W2 W2 W2 . . .
STRB,
STRB0,
STRB1
bus
Cw Cw (3.5 + C r + 2 + C w) T + .5 ( T – 1)
{
(’C30 only)
Source
R1 R1 R1 R1 I R2 R2 R2 R2 I R3 R3 R3 R3 I R4 R4 R4 R4
Source
IOSTRB
Cr Cr Cr Cr (3 + Cr + 2 + Cw) + (2 + Cw + max[1, Cr – Cw + 1])
(
T –1)
Destination W1 W1 W1 W1 W2 W2 W2 W2 W3 W3 W3 W3
( T –1)
STRB bus Cw Cw Cw
Legend:
T = Number of transfers W = Single-cycle writes
Cr = Source-read wait states R n = Multicycle reads
Cw = Destination-write wait states W n = Multicycle writes
R = Single-cycle reads I = Internal register cycle
†
Write followed by read incurs in one extra half-cycle.