Texas Instruments TMS320C3x - Manual (Page 203)

Interlocked Operations
7-19 Program Flow Control
Example 7–12. Code to Synchronize Two TMS320C3x Devices at the Software Level
N
Code for ’C3x #2 Code for ’C3x #1 Time
O
(WAIT)
SIGI
SIGI Synchronization occurs
7.4.3 Pipeline Effects of Interlocked Instructions
Before performing an interlocked instruction, the XF0 pin must be configured as
an output pin and the XF1 pin must be configured as an input pin through the
IOF register (see subsection 3.1.10,
I/O Flag Register (IOF), on page 3-16).
After the XF0 and XF1 pins are configured, no interlocked instruction can occur
in the following two instructions.