Texas Instruments TMS320C3x - Manual (Page 218)

Interrupts
7-34
Figure 7–6. CPU Interrupt Processing
DMA proceeds according
to SYNC bits
If enabled,
interrupt is
a DMA interrupt
Clear interrupt flag
DMA continues
CPU starts executing ISR routine
Complete all fetched instructions
PC
←
interrupt vector
PC
→
*(++SP)
Clear interrupt flag
Disable interrupts
GIE
←
0
If enabled,
interrupt is
a CPU interrupt
Is an enabled
interrupt set
?
No
Yes
Note: CPU and DMA Interrupts
CPU interrupts are acknowledged (responded to by the CPU) on instruction
fetch boundaries only. If instruction fetches are halted because of pipeline
conflicts or execution of RPTS loops, CPU interrupts are not acknowledged
until the next instruction fetch.