Texas Instruments TMS320C3x - Manual (Page 530)

ASH Arithmetic Shift
13-72
Status Bits These condition flags are modified only if the destination register is R7 – R0.
LUF Unaffected
LV 1 if an integer overflow occurs; unchanged otherwise
UF 0
N MSB of the output
Z 1 if a 0 result is generated; 0 otherwise
V 1 if an integer overflow occurs; 0 otherwise
C Set to the value of the last bit shifted out; 0 for a shift count of 0
OVM Operation is not affected by OVM bit value.
Example 1 ASH R1,R3
Before Instruction After Instruction
R1 00 0000 0010 R1 00 0000 0010
R3 00 000A E000 R3 00 E000 0000
LUF 0 LUF 0
LV 0 LV 1
UF 0 UF 0
N 0 N 1
Z 0 Z 0
V 0 V 1
C 0 C 0
16
Example 2 ASH @98C3h,R5
Before Instruction After Instruction
R5 00 AEC0 0001 R5 00 FFFF FFAE
DP 80 DP 80
LUF 0 LUF 0
LV 0 LV 0
UF 0 UF 0
N 0 N 1
Z 0 Z 0
V 0 V 0
C 0 C 1
Data memory
8098C3h 0FFE8 8098C3h 0FFE8 –24 –24
Mode Bit