Texas Instruments TMS320C3x User Manual

Page 431

DMA Controller

12-52

At reset, each DMA-channel control register is set to 0. This makes the DMA
channels lower-priority than the CPU, sets up the source address and destination
address to be calculated through linear addressing, and configures the DMA
channel in the unified mode.

Figure 12–35. Memory-Mapped Locations for DMA Channels

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Address

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Register

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808000h

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DMA 0 global control

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808004h

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DMA 0 source address

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808006h

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DMA 0 destination address

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808008h

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DMA 0 transfer counter

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808010h

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DMA 1 global control†

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808014h

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DMA 1 source address†

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808016h

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DMA 1 destination address†

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808018h

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DMA 1 transfer counter†

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† ’C32 only