Texas Instruments TMS320C3x - Manual (Page 546)

CMPF Compare Floating-Point Value
13-88
Syntax CMPF src, dst
Operation dst – src
Operands src general addressing modes (G):
0 0 register (R n, 0
≤
n
≤
7)
0 1 direct
1 0 indirect (disp = 0–255, IR0, IR1)
1 1 immediate
dst register (Rn, 0
≤
n
≤
7)
Opcode
31 24 23 16 8 7 0 15
0 0 0 0 0 1 0 dst 0 0 G src
Description The src operand is subtracted from the dst operand. The result is not loaded
into any register, which allows for nondestructive compares. The dst and src
operands are assumed to be floating-point numbers.
Cycles 1
Status Bits These condition flags are modified for all destination registers (R27 – R0).
LUF 1 if a floating-point underflow occurs; unchanged otherwise
LV 1 if a floating-point overflow occurs; unchanged otherwise
UF 1 if a floating-point underflow occurs; 0 otherwise
N 1 if a negative result is generated; 0 otherwise
Z 1 if a 0 result is generated; 0 otherwise
V 1 if a floating-point overflow occurs; 0 otherwise
C Unaffected
OVM Operation is not affected by OVM bit value. Mode Bit