Texas Instruments TMS320C3x - Manual (Page 707)

Bitwise-Exclusive OR XOR
13-249 Assembly Language Instructions
Syntax XOR src, dst
Operation dst XOR src
→
dst
Operands src general addressing modes (G):
0 0 register (R n, 0
≤
n
≤
27)
0 1 direct
1 0 indirect (disp = 0–255, IR0, IR1)
1 1 immediate
dst register (Rn, 0
≤
n
≤
27)
Opcode
31 24 23 16 8 7 0 15
0 0 0 1 1 0 1 1 0 dst G src
Description The bitwise-exclusive OR of the src and dst operands is loaded into the dst
register. The dst and src operands are assumed to be unsigned integers.
Cycles 1
Status Bits These condition flags are modified only if the destination register is R7 – R0.
LUF Unaffected
LV Unaffected
UF 0
N MSB of the output
Z 1 if a 0 output is generated; 0 otherwise
V 0
C Unaffected
OVM Operation is not affected by OVM bit value.
Example XOR R1,R2
Before Instruction After Instruction
R1 00 000F FA32 R1 00 000F F412
R2 00 000F F5C1 R2 00 0000 0FF3
LUF 0 LUF 0
LV 0 LV 0
UF 0 UF 0
N 0 N 0
Z 0 Z 0
V 0 V 0
C 0 C 0
Mode Bit