Texas Instruments TMS320C3x - Manual (Page 632)

NEGF Negate Floating-Point Value
13-174
Syntax NEGF src, dst
Operation 0 – src
→
dst
Operands src general addressing modes (G):
0 0 register (R n, 0
≤
n
≤
7)
0 1 direct
1 0 indirect (disp = 0–255, IR0, IR1)
1 1 immediate
dst register (Rn, 0
≤
n
≤
7)
Opcode
31 24 23 16 8 7 0 15
0 0 0 0 1 1 1 1 0 dst G src
Description The difference of the 0 and src operands is loaded into the dst register. The
dst and src operands are assumed to be floating-point numbers.
Cycles 1
Status Bits These condition flags are modified only if the destination register is R7 – R0.
LUF 1 if a floating-point underflow occurs; unchanged otherwise
LV 1 if a floating-point overflow occurs; unchanged otherwise
UF 1 if a floating-point underflow occurs; 0 otherwise
N 1 if a negative result is generated; 0 otherwise
Z 1 if a 0 result is generated; 0 otherwise
V 1 if a floating-point overflow occurs; 0 otherwise
C Unaffected
OVM Operation is affected by OVM bit value. Mode Bit